1. Field of the Invention
The present invention relates to an interface circuit, more particularly, to a capacitor interface circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram of the conventional capacitor interface circuit 100. FIG. 2 is an operation timing chart of the capacitor interface circuit 100 shown in FIG. 1. Referring to FIGS. 1 and 2, the capacitor interface circuit 100 includes a capacitor under test (CUT) Cin, six switches 101 through 106, a fully differential amplifier 107, and two feedback capacitors 108 and 109 with the same capacitance, wherein the fully differential amplifier 107 has a common mode input terminal receiving a common mode voltage Vcm, a positive and a negative input terminals, and a positive and a negative output terminals. The switches 101 through 104 are respectively and sequentially controlled by the control signals CTR1 through CTR4; and the switches 105 and 106 are simultaneously controlled by the reset signal RES.
Conventional, the capacitance of the CUT Cin can be obtained by calculating the formula Cin=Vout/(VREFP−VREFN)*Cint1, wherein VREFP is a positive reference voltage, VREFN is a negative reference voltage, Vout is an output voltage of the capacitor interface circuit 100, and Cint1 is the capacitance of the feedback capacitor 108. In general, the positive reference voltage VREFP, the negative reference voltage VREFN, and the capacitance Cint1 of the feedback capacitor 108 are all given parameters, so the capacitance of the CUT Cin can be calculated by obtaining the output voltage Vout of the capacitor interface circuit 100.